1. Technical Field
The present invention relates to a semiconductor integrated circuit and a method of controlling an internal voltage of the same.
2. Related Art
A semiconductor integrated circuit uses various voltage levels, and power can be divided into two main types: external power (VDD and VSS) and internal power (VPP and VBB).
In other words, external power is supplied by an apparatus having a semiconductor integrated circuit mounted thereon, and internal power is supplied by converting the external power in the semiconductor integrated circuit.
In ascending order, the voltage levels are VPP, VDD, VSS, and VBB. VBB is a reverse bias voltage having an absolute value larger than that of the ground voltage VSS.
VPP is essentially used in a word line driver and a data-out driver in order to compensate for threshold voltage loss in a transistor constituting a memory cell of an integrated circuit. VPP is generated by boosting VDD and has a value larger than the sum of VDD and the threshold voltage VT.
The stability of the above-mentioned internal power has a great impact on the reliability and current consumption of a semiconductor integrated circuit. Therefore, in the design of a semiconductor integrated circuit, it is important to provide a stable supply of power within a predetermined range by controlling the power supply.
Hereinafter, a semiconductor integrated circuit according to the related art will be described with reference to FIGS. 1 to 4.
FIG. 1 is a block diagram showing the structure of a semiconductor integrated circuit according to the related art. FIG. 2 is a circuit diagram showing the internal structure of a VBB detector 14 of FIG. 1. FIG. 3 is a cross-sectional view showing a well bias of the semiconductor integrated circuit. FIG. 4 is a waveform view showing change in VPP and VBB according to the related art.
In the semiconductor integrated circuit according to the related art, as shown in FIG. 1, a structure for controlling VPP and a structure for controlling VBB are separate from each other.
The structure for controlling VPP includes a elevated voltage detector (hereinafter, referred to as a VPP detector) 11, a VPP oscillator (VPP OSC) 12, and a elevated voltage pump (hereinafter, referred to as a VPP pump) 13.
The VPP detector 11 detects whether the level of VPP is lower than a predetermined value and outputs an enable signal PPEN (for example, a high-level signal) to drive the VPP pump 13.
The VPP oscillator 12 generates a pulse during a period when the enable signal PPEN output by the VPP detector 11 is at a high level.
The VPP pump 13 performs a pumping operation using a pulse OSCPP output from the VPP oscillator 12 so as to raise the level of VPP.
The structure for controlling VBB includes a substrate bias voltage detector (hereinafter, referred to as a VBB detector) 14, a VBB oscillator (VBB OSC) 15, and a substrate bias voltage pump (hereinafter, referred to as a VBB pump) 16.
The VBB detector 14 detects whether the level of VBB is higher than a predetermined value, and outputs an enable signal BBEN (for example, a ‘high-level’ signal) to drive the VBB pump 16.
An example of the internal structure of the VBB detector 14 is shown in FIG. 2, and is composed of two PMOS transistors P1 and P2 and two inverters IV1 and IV2. The VBB detector 14 is operated so that a control signal for the PMOS transistor P2 varies depending on the VBB level and the state of the output signal BBEN is determined to be ‘high’ or ‘low’ according to a difference between the control signals for PMOS transistors P1 and P2.
The VBB oscillator 15 generates a pulse OSCBB during a period when the enable signal BBEN output by the VBB detector 14 is at the high level.
The VBB pump 16 performs a pumping operation using the pulse OSCBB output from the VBB oscillator 15 such that the level of VBB is lowered. In other words, since VBB is a reverse bias, the pumping operation is performed such that the level of VBB increases in a negative direction.
The VPP pump 13 is designed to have a size larger than the VBB pump 16 so as to generate a VPP having a level higher than that of VDD (external voltage). Furthermore, the response time of the VBB detector 14 is longer than that of the VPP detector 11. That is, the response of the VBB detector 14 is later than that of the VPP detector 11.
A well bias of the semiconductor integrated circuit is configured as shown in FIG. 3. That is, an N-well to which the VPP is applied and a P-well to which the VBB is applied are adjacent to each other.
Therefore, the probability that coupling noise of VPP and VBB will occur due to a junction capacitor between the adjacent wells is very high.
In other words, as shown in FIG. 4, the VPP level rises when the VPP pump 13 operates, is gradually lowered after the operation of the VPP pump stops, rises when the VPP pump 13 operates again due to the set value detection of the VPP detector 11, and is then gradually lowered over time. This procedure is repeated.
When the level of VPP rises in sections A and B due to the operation of the VPP pump 13, the level of VBB also rises due to the above-mentioned coupling noise.
Even though the VBB pump 16 operates in section B to lower the level of VBB, since the VPP pump 13 is still operating, the VBB level increases a little. The level of VBB normally drops in section C, when the operation of the VPP pump 13 completely stops, until the operation of the VBB pump 16 stops.
In the semiconductor integrated circuit according to the related art, the size of the VPP pump 13 is larger than that of the VBB pump 16 and the response speed of the VBB detector 14 is slower than that of the VPP detector 11. Furthermore, coupling noise occurs due to a junction capacitor formed between the power supplies of the internal power supplies applied to adjacent regions.
As a result, when a high-level power supply voltage VPP rises, a relatively low-level substrate bias voltage VBB rises together with the high-level power supply voltage to deviate from a target value, resulting in an unstable power supply voltage.
Therefore, the semiconductor integrated circuit according to the related art has the following problems:
First, the operational reliability of the semiconductor integrated circuit deteriorates.
Second, current loss of a transistor constituting a memory cell of the semiconductor integrated circuit increases.